Oferta wygasa za:84 dni
Tryb pracyZdalna
Rodzaj umowyKontrakt B2B
Tryb rekrutacjiRekrutacja stacjonarna
Wymiar etatuPełny etat
BranżaInżynieria
Your responsibilities
- Design configurable and ultra-low-latency RTL modules.
- Optimize FPGA implementations for logic utilization and timing performance.
- Take end-to-end ownership of the development process, from architecture and microarchitecture through design and implementation.
- Understand system and software requirements to implement efficient HW-SW interfaces
Our requirements
- B.Sc. in Electrical Engineering, Computer Engineering, or equivalent background.
- At least 4 years of professional experience.
- Proven experience in RTL design using SystemVerilog.
- Strong knowledge of digital logic design and FPGA development.
- Experience with tools such as Vivado and VCS is an advantage.
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